1. Field of the Invention
The present invention relates to a semiconductor device and a method of testing the semiconductor device. In particular, the invention relates to a semiconductor device including a clock control circuit that controls clock supply to an internal circuit of the semiconductor device and a method of testing the semiconductor device.
2. Description of Related Art
In recent years, integrated circuits such as LSI (Large Scale Integration) have proceeded toward a large-scale circuit, advanced functions, and miniaturization of elements. Further, a problem about a failure regarding a LSI's operational speed is not negligible. To test a failure regarding a speed, functional tests including a delay test should be carried out. The related art aiming at testing operations of the LSI is disclosed in Japanese Unexamined Patent Publication No. 2002-196046.
However, if the related art is applied to the recent LSI with a large scale circuit, a numerous number of test patterns need to be generated for the functional test. Alternatively, to perform the functional test with fewer test patterns, many terminals should be added. Thus, test period and cost increase due to testing with a numerous number of test patterns or a chip area increases due to the added terminals, resulting in a problem of increasing a chip cost.
A test method that limits the number of terminals is described next as Related Art 1. FIG. 19 shows a target semiconductor device. As shown in FIG. 19, the semiconductor device includes external clock domains operating in response to an externally supplied user clock and internal clock domains operating based on an internally generated clock. Further, the external clock domains and the internal clock domains may be classified into groups according to clock.
In the Related Art 1, the external clock domains are classified into an external clock domain 101 operating with a frequency of 10 MHz, an external clock domain 102 operating with a frequency of 20 MHz, and external clock domains 103, 104, and 105 operating with a frequency of 20 MHz. Further, user clock terminals U-CLK101 to U-CLK105 and user data input terminals D101 to D105 of the external clock domains 101 to 105 are connected together. The user clock terminals U-CLK101 to U-CLK105 supply a clock to the external clock domains 101 to 105. The user data input terminals D101 to D105 supply a data signal to the external clock domains 101 to 105.
In the Related Art 1, the internal clock domains are classified into internal clock domains 111 and 112 operating with a frequency of 10 MHz, and internal clock domains 113, 114, and 115 operating with a frequency of 20 MHz. Further, the internal clock domains 111 to 115 have interdependence through a data path. For example, the internal clock domain 111 operates based on data from the internal clock domain 113. The internal clock domain 112 operates based on data from the internal clock domain 111. The internal clock domain 113 operates based on data from the internal clock domain 115. The internal clock domain 114 operates based on data from the internal clock domain 113.
The functional test for the aforementioned semiconductor device is carried out in such a manner that the external clock domains 101 to 105 get logic circuits to operate based on a clock signal that is input through the user clock terminals U-CLK101 to U-CLK105 and a data signal that is input through the user data input terminals D101 to D105. The functional test for the internal clock domains 111 to 115 is performed in such a manner that a scan clock signal used in the internal clock domain is input from a scan clock supply terminal SCKin and the internal clock domains 111 to 115 operate based on the scan clock signal. In general, to input the scan clock signal to the internal clock domains 111 to 115 this way, a DFT (Design For Test) circuit including the scan clock supply terminal SCKin and a selector is added.
FIG. 20 is a flowchart of a procedure of adding the DFT circuit. As shown in FIG. 20, DFT-circuit preinsertion circuit information F101 is input first (step S101). Next, an internal clock domain is extracted from the DFT-circuit preinsertion circuit information F101 (step S102). Subsequently, a selector selecting a scan clock signal SCK and an internal clock signal and supplying the selected ones to the internal clock domain is added to the circuit information based on the extracted internal clock domain (step S103). Further, one scan clock supply terminal SCKin is added to the DFT-circuit preinsertion circuit information F101 (step S104). The scan clock supply terminal SCKin and the selector added in steps S103 and S104 are connected with each other (step S105). After that, generated DFT-circuit postinsertion circuit information F102 is output (step S106). Referring to this flowchart, information about the selector and the scan clock supply terminal SCKin are added to the circuit information. FIG. 21 is a block diagram of a semiconductor device corresponding to an internal clock domain portion where the information about the selector and the scan clock supply terminal SCKin are added.
As shown in FIG. 21, in the semiconductor device with the added information about the selector and the scan clock supply terminal SCKin, the internal clock domains 111 to 115 are connected with selectors 121 to 125. The selectors 121 to 125 are supplied with a test mode control signal AMC designating which of signals input to the selectors is output. Further, a corresponding internal clock is input to “0” input of the selectors 121 to 125, and “1” input is connected with one scan clock supply terminal SCKin.
FIG. 22 is a flowchart of a procedure of generating a test pattern used in the functional test for the internal clock domain of the semiconductor device as shown in FIG. 21. As shown in FIG. 22, the test pattern is generated as follows. First, it is determined whether or not there are internal clock domains requiring a test pattern (step S107). If it is determined that internal clock domains requiring a test pattern exist in step S107, a target internal clock domain is selected from the internal clock domains (step S108). Subsequently, a test pattern masking process is carried out on internal clock domains not requiring a test pattern (step S109). After that, a test pattern of the internal clock domain requiring a test pattern is automatically generated with ATPG (Automatic Test Pattern Generation) (step S110). After the ATPG is carried out to generate a test pattern, the control returns to step S107. The processes of steps S107 to S110 are repeated until a test pattern is generated for all internal clock domains. If it is determined that there is no internal clock domain requiring a test pattern in step S107, test pattern generation is finished.
FIG. 23 shows a test pattern example generated with reference to the flowchart of FIG. 22. As shown in FIG. 23, test patterns corresponding to the internal clock domains 111 to 115 are generated. In the Related Art 1, five patterns are generated. Here, in these test patterns, denoted by “X” is an off state value for stopping circuit operations. For example, “Low” is set. The off state value is generated through the masking process in step S109 of the flowchart of FIG. 22. The functional test of the semiconductor device in the Related Art 1 is carried out by inputting the test patterns of FIG. 23 into the internal clock domains 111 to 115 through a scan chain circuit (not shown).
Meanwhile, as another example of the functional test of theh semiconductor device of FIG. 19, a testing method that limits the number of test patterns is described next. This testing method is referred to as Related Art 2. FIG. 24 is a flowchart of a procedure of adding a DFT circuit in the Related Art 2.
As shown in FIG. 24, in the Related Art 2, DFT-circuit preinsertion circuit information F121 is input first (step S121) Next, an internal clock domain is extracted from the DFT-circuit preinsertion circuit information F121 (step S122). Subsequently, a selector selecting a scan clock signal SCK and an internal clock signal and supplying the selected ones to the internal clock domain is added to the circuit information (step S123). Further, plural scan clock supply terminals SCKin are added to the DFT-circuit preinsertion circuit information F121 (step S124). Plural scan clock supply terminals SCKin and the selector added in steps S123 and S124 are connected together (step S125). After that, the generated DFT-circuit postinsertion circuit information F122 is output (step S126). Referring to the flowchart, information about the selector and the scan clock supply terminals SCKin are added to the circuit information. FIG. 25 shows a semiconductor device where the information about the selector and the scan clock supply terminal SCKin are added.
As shown in FIG. 25, in the semiconductor device added with the information about the selector and the scan clock supply terminal SCKin in the Related Art 2, the selectors 121 to 125 are connected with the internal clock domains 111 to 115, respectively. A test mode control signal AMC indicating which of the signals input to the selectors is input to the selectors 121 to 125. Further, a corresponding internal clock is input to “0” input of the selectors 121 to 125, and “1” input is connected with a corresponding one of the scan clock supply terminals SCKin.
FIG. 26 is a flowchart of a procedure of generating a test pattern used in a functional test of an internal clock domain of the semiconductor device of FIG. 25. As shown in FIG. 26, in the Related Art 2, a between the internal clock domains is extracted first (step S127). Subsequently, in accordance with the data-path-based interdependence extracted in step S127, internal clock domains not influenced by each other are grouped, and an internal clock domain group is extracted (step S128).
After that, it is determined whether or not there are internal clock domain groups requiring a test pattern (step S129). If it is determined that internal clock domain groups requiring a test pattern exist in step S129, a target internal clock domain group is selected from the internal clock domain groups (step S130). Subsequently, a test pattern masking process is carried out on internal clock domain groups not requiring a test pattern (step S131). After that, a test pattern of the internal clock domain group requiring a test pattern is automatically generated with ATPG (Automatic Test Pattern Generation) (step S132). After the ATPG is carried out to generate a test pattern, the control returns to step S129. The processes of steps S129 to S132 are repeated until a test pattern is generated for all internal clock domain groups. If it is determined that there is no internal clock domain group requiring a test pattern in step S129, the test pattern generation is finished.
FIG. 27 shows a test pattern example generated with reference to the flowchart of FIG. 26. As shown in FIG. 27, there are three test patterns corresponding to three groups, first to third groups obtained by classifying internal clock domains according to data-path-based interdependence between the internal clock domains. A functional test of the semiconductor device in the Related Art 2 is carried out by inputting the test patterns of FIG. 27 into the internal clock domains 111 to 115 through a scan chain circuit (not shown).
However, in the testing method for the semiconductor device in the Related Art 1, although the number of added terminals is 1, the number of generate test patterns increases. This leads to a problem of increasing a test period or test cost.
Further, in the testing method for the semiconductor device in the Related Art 2, the number of test patterns can be limited, but the number of added terminals increases, resulting in a problem that chip area and cost increase.